The present invention relates to a method of producing a semiconductor integrated circuit device and a semiconductor integrated circuit device, particularly to an effective technique adapted to manufacture of a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory).
In a recent large DRAM of 64 or 256 megabits (Mbits), in forming a contact hole for connecting a bit line or information storage capacitive element to a semiconductor substrate in a space between gate electrodes of a miniaturized memory cell selecting MISFET, the top and sidewalls of the gate electrodes are covered with a silicon nitride film, a silicon oxide film burying the space between the gate electrodes is formed over the silicon nitride film including the space between the gate electrodes and then a contact hole is formed utilizing the different of an etching rate between the silicon oxide film and the silicon nitride film. At that time, the Self Align Contact (SAC) technique is adopted in which a contact hole is opened self-aligningly to the space between the gate electrodes utilizing the different of an etching rate between the silicon oxide film and the silicon nitride film.
As for the SAC technique, it is described in Japanese Patent Laid-Opens No. 135781/1999 and No. 68064/1999, for example. In Japanese Patent Laid-Open No. 135781/1999, it discloses a technique in which a contact hole is opened by the SAC technique and then a sidewall insulating film for protecting an interlayer insulating film is formed in wet etching for removing a natural oxide film that is formed inside the contact hole. Additionally, in Japanese Patent Laid-Open No. 68064/1999, it discloses a technique in which a polycrystalline silicon film is used as an etching stopper in forming a contact hole by the SAC technique and a sidewall comprised of a silicon oxide film is formed on the inner walls of the contact hole to prevent leakage from being generated through the polycrystalline silicon film after opening the contact hole.
However, the inventors found the following problems in the Self Align (SAC) technique described above.
More specifically, as an aspect ratio (a ratio between a space height and a space width) of the space between the gate electrodes is increased, voids tend to be generated in the silicon oxide film burying the space. Additionally, when the space is buried with a coating film such as an organic SOG film or inorganic SOG film or a low dielectric constant insulating film having a dielectric constant of three or less, voids are hardly generated right after burying. However, these films are liable to wet etching and thus voids might be generated due to the cleaning process after forming the contact holes.
When the voids are generated, a problem arises that the adjacent contact holes are short-circuited by a conductive film through the voids when the contact holes are buried with a conductive film such as a polycrystalline silicon film after forming the contact holes.
As one scheme to avoid such a problem, it is considered to adopt a technique in which a sidewall protecting film comprised of a silicon nitride film or silicon oxide film is deposited over the sidewalls of contact holes after forming the contact holes and thereby openings of the voids are blocked or void generation is prevented beforehand. In this case, the sidewall protecting film is also deposited over the bottom of the contact holes. Thus, the sidewall protecting film deposited over the bottom of the contact holes is removed using etchback and a semiconductor substrate is to be exposed in the bottom of the contact holes.
However, when the technique of depositing the sidewall protecting film over the sidewalls of the contact hole is adopted, a problem occurs that an amount of the semiconductor substrate cut is increased in the bottom of the contact hole because the etching process for removing the sidewall protecting film in the bottom of the contact hole is increased. Furthermore, a problem arises that the shallow junction of a diffused layer cannot be coped because the amount of the semiconductor substrate cut is increased in the bottom of the contact hole. Moreover, a problem occurs that contact resistance in the bottom of the contact hole is increased because of the cut of the semiconductor substrate due to etching or damage contamination.
Besides, the sidewall protecting film decreases the coverage at the corners in the bottom of the contact hole. Thus, the film thickness becomes thinner in the lower part of the sidewalls of the contact hole and sidewall protection is not achieved sufficiently. Therefore, a problem arises that etching the interlayer insulating film proceeds at that portion and the adjacent contact holes are short-circuited due to the conductive film burying the contact hole.
The purpose of the invention is to provide a technique capable of reducing an amount of a semiconductor substrate cut due to etching in the bottom of a hole part in a semiconductor integrated circuit device having hole parts formed by the SAC technique.
Additionally, another purpose of the invention is to provide a technique capable of preventing the adjacent hole parts from being short-circuited due to a conductive film burying the hole parts in the semiconductor integrated circuit device having the hole parts formed by the SAC technique.
The aforesaid and other purposes and novel features of the invention will be apparent from the description of the specification and accompanying drawings.
The followings are the brief summary of representative inventions among the inventions disclosed in the specification.
That is, the invention includes the steps of: forming a first conductive film over a semiconductor substrate and then forming a first insulating film over the first conductive film; forming a plurality of gate electrodes and a cap insulating film covering the upper part of the gate electrodes by etching the first conductive film and the first insulating film; forming a third insulating film over the semiconductor substrate including the sidewalls and upper part of the cap insulating film; forming a fourth insulating film over the third insulating film; forming a first hole part by etching the fourth insulating film; etching the third insulating film exposed in the bottom of the first hole part by a predetermined amount after the step of forming the first hole part; forming a fifth insulating film having a film thickness not fully burying a space between the plurality of the gate electrodes over the fourth insulating film and the sidewalls and bottom of the first hole part; and forming a second hole part by applying anisotropic etching to the fifth insulating film. Etching conditions are different in the step of etching the fourth insulating film and the step of etching the third insulating film.
Additionally, the invention includes the steps of: forming a first conductive film over a semiconductor substrate and then forming a first insulating film over the first conductive film; forming a plurality of gate electrodes and a cap insulating film covering the upper part of the gate electrodes by etching the first conductive film and the first insulating film; forming a second insulating film by oxidizing the sidewalls of the plurality of gate electrodes and the surface of the semiconductor substrate between the plurality of gate electrodes; forming a third insulating film over the semiconductor substrate including the upper part of the second insulating film and the upper part and sidewalls of the cap insulating film; forming a fourth insulating film over the third insulating film; forming a first hole part by etching the fourth insulating film; etching the third insulating film exposed in the bottom of the first hole part using the second insulating film as an etching stopper after the step of forming the first hole part; forming a fifth insulating film having a film thickness not fully burying the space between the plurality of gate electrodes over the fourth insulating film and the sidewalls and bottom of the first hole part; applying anisotropic etching to the fifth insulating film to expose the second insulating film; and forming a second hole part by removing the second insulating film exposed from the fifth insulating film. Etching conditions are different in the step of etching the fourth insulating film and the step of etching the third insulating film.
Furthermore, the invention includes the steps of: forming a first conductive film over a semiconductor substrate and then forming a first insulating film over the first conductive film; forming a plurality of gate electrodes and a cap insulating film covering the upper part of the gate electrodes by etching the first conductive film and the first insulating film; forming a third insulating film over the semiconductor substrate including the sidewalls and upper part of the cap insulating film; forming a fourth insulating film over the third insulating film; forming a first hole part by etching the fourth insulating film; etching the third insulating film exposed in the bottom of the first hole part by a predetermined amount after the step of forming the first hole part; forming a fifth insulating film having a film thickness not fully burying a space between the plurality of the gate electrodes over the fourth insulating film and the sidewalls and bottom of the first hole part; forming a second hole part by applying anisotropic etching to the fifth insulating film; and forming a second conductive film inside the second hole part. The third insulating film is overlapped with the fifth insulating film in the bottom of the second hole part.
Moreover, the invention includes the steps of: forming a first conductive film over a semiconductor substrate and then forming a first insulating film over the first conductive film; forming a plurality of gate electrodes and a cap insulating film covering the upper part of the gate electrodes by etching the first conductive film and the first insulating film; forming a second insulating film by oxidizing the sidewalls of the plurality of gate electrodes and the surface of the semiconductor substrate between the plurality of gate electrodes; forming a third insulating film over the semiconductor substrate including the upper part of the second insulating film and the sidewalls and upper part of the cap insulating film; forming a fourth insulating film over the third insulating film; forming a first hole part by etching the fourth insulating film; etching the third insulating film exposed in the bottom of the first hole part using the second insulating film as an etching stopper after the step of forming the first hole part; forming a fifth insulating film having a film thickness not fully burying the space between the plurality of gate electrodes over the fourth insulating film and the sidewalls and bottom of the first hole part; applying anisotropic etching to the fifth insulating film to expose the second insulating film; forming a second hole part by removing the second insulating film exposed from the fifth insulating film; and forming a second conductive film inside the second hole part. The third insulating film is overlapped with the fifth insulating film in the bottom of the second hole part.
Besides, the invention includes:
(a) a plurality of gate electrodes formed over a semiconductor substrate;
(b) a cap insulating film formed over the plurality of gate electrodes;
(c) a second hole part formed between the plurality of gate electrodes, the second hole part reaching the semiconductor substrate;
(d) a third insulating film configuring at least a part of the sidewalls of the cap insulating film, the sidewalls of the gate electrodes and the sidewalls of the second hole part;
(e) a fourth insulating film formed over the third insulating film;
(f) a fifth insulating film configuring the sidewalls of the second hole part; and
(g) a second conductive film formed inside the second hole part. The third insulating film is overlapped with the fifth insulating film in the bottom of the second hole part.
According to the invention, the etching conditions are changed in the midway of the formation in forming the second hole part reaching the semiconductor substrate by etching. Therefore, the semiconductor substrate underlying the bottom of the second hole part can be prevented from being cut.
Additionally, according to the invention, the semiconductor substrate can be prevented from being cut by etching in forming the second hole part reaching the semiconductor substrate. Therefore, a damaged layer due to etching can be prevented from generating in the semiconductor substrate.
Furthermore, according to the invention, an insulating film having a main component of silicon oxide can be prevented from being exposed in the sidewalls of the second hole part reaching the semiconductor substrate. Thus, the insulating film can be prevented from being wet etched by the cleaning process.
Moreover, according to the invention, the insulating film having a main component of silicon oxide can be prevented from being wet etched from the sidewalls of the second hole part. Therefore, the adjacent second hole parts can be prevented from being short-circuited.